In electrically erasable and programmable read only memory (EEPROM) devices, the most widely used floating gate EEPROM cell may erase and program data by utilizing Fowler-Nordheim (F-N) tunnelling of electrons through a thin gate oxide. One bit of such prior-art EEPROM cells is composed of a select transistor for selecting the bit according to input address and a sense transistor having a floating gate for attracting or extracting electrons thereto or therefrom according to a program (or write) or an erase mode upon selection of the bit. Prior EEPROM devices having such EEPROM cells have advantages capable of performing program, erase and read operations in byte (8 bits) and using with a single +5 volts power supply. However, since the EEPROM cell employs two transistors per bit, employing such cells in high density EEPROR devices is undesirable for the scaling-down of chip.
To solve such problem, EEPROM device with NAND cells (hereinafter referred to as memory strings) is disclosed in 1988 SYMPOSIUM ON VLSI CIRCUIT. DIGEST OF TECHNICAL PAPERS, pages 33-34. FIG. 1 shows a portion of an equivalent circuit for a memory array of cells of the EEPROM device with memory strings. The memory array 10 comprises a plurality of bit lines BL1, BL2, . . . , represented by parallel column lines, and a plurality of memory strings MS11, MS12, . . . which are arranged in a matrix form of mutually parallel rows and columns and coupled between each bit line and ground. Each of memory strings is composed of a string select MOS transistor ST whose drain is coupled to the corresponding bit line, a ground select MOS transistor GT whose source is coupled to ground and 8-bit floating gate MOS transistors MC1 to MC8 whose drain-source paths are coupled in series between the source of the transistor ST and the drain of the transistor GT. Gates of transistors ST, each control gate of floating gate transistors MC1 to MC8 and gates of transistors GT are respectively coupled to a string select lins SSL1, word lines WL11 to WL18 and ground select line GSL1 which are parallel lines in rows.
Operation modes of the EEPROM device will be described with reference to FIG. 1.
Erase operation is of a flash erase which is simultaneously erasing data of whole memory cells. Such flash erase may be carried out by applying 5 volts to string and ground select lines SSL1 and GSL1 to turn on transistors ST and GT, applying an erase voltage of 13 volts to all word lines WL11 to WL18 and grounding all bit lines BL1, BL2, . . . . By the application of such voltages, each floating gate transistor is erased to an enhancement mode MOS transistor by F-N tunelling of electrons from its drain to its floating gate.
Program operation may be performed for each word line after the flash erase. For example, explanation will be made for programming a memory cell MC4 in the memory string MS11. The programming of the memory cell MC4 may be achieved by applying a pass voltage of 20 volts to the string select line SSL1 as well as unselected word lines WL11 to WL13 between the string select line SSL1 and the selected word line WL14 (pass word lines), applying ground (0 volt) to word lines WL14 to WL18 and the ground select line GSL1, and applying a program voltage of 20 volts to the bit line BL1. The program voltage on the bit line BL1 is transferred to the drain of the selected transistor MC4 through the string select MOS transistor ST and transistors MC1 to MC3 which are all turned on in the memory string MS11. Then, the transistor MC4 is programmed to a depletion mode floating gate MOS transistor by F-N tunelling of electrons from its floating gate to its drain.
Read operation of a memory cell MC4 in the memory string MS11 may be performed by applying ground to a selected word line WL14 and applying 5 volts to string and ground select lines SSL1 and GSL1, all unselected word lines WL11 to WL13 and WL15 to WL18, and the bit line BL1. When the memory cell MC4 was erased as enhancement mode transistor, there will be no current flowing on the bit line BL1 because of OFF-state of the memory cell MC4. Alternatively, when the memory cell MC4 was programmed as depletion mode transistor, current flowing on the bit line BL1 will be present because of ON-state of the memory cell MC4. Therefore, a sense amplifier coupled to the bit line BL1 may read out data in the selected memory cell MC4 by detecting the current flowing on the bit line BL1.
This EEPROM device has the following disadvantages. Since the pass voltage (20 volts), which is, during a program operation, applied to control gates of memory cells coupled to the pass word lines for transferring the program voltage (20 volts) on the selected bit line to the drain of the selected memory cell, is even higher than the erase voltage (13 volts) required for erasing all memory cells during an erase operation, all memory cells associated with pass word lines and unselected bit lines may be either automatically erased or over-erased. Therefore, disturbance of memory cells may be occurred.
Another problem is to require a contact area with large size to interconnect between each memory string and the corresponding bit line. Under the location of memory strings underneath bit lines, each contact area occupying a large area gives limit to the scaling-down of memory cells in the row direction. Therefore, the scaling down of the memory array is restricted.